Storing immediate data of immediate instructions in a data table

ABSTRACT

An efficient coding scheme is disclosed. The coding provides for the separation of immediate data from the instruction stream. A static flow analysis determines the immediate data in the program and assigns it a location for storage in a data table. The flow analysis also generates information directing the processor to the location of the immediate data in the data-order table. When an immediate instruction is encountered during execution, the processor retrieves the immediate data from the data-order table.

FIELD OF THE INVENTION

The invention generally relates to processors and, more particularly, toimproving coding efficiency in processors.

BACKGROUND OF THE INVENTION

In general, a digital computer performs tasks defined by a list ofinternally stored instructions. The list of instructions or computercodes, which is referred to as a program, is stored in the computer'smain memory. To perform a given computational task, the centralprocessing unit or processor of the digital computer fetches individualinstructions of the program for execution. A program counter within thecomputer points to the next instruction to be executed.

The length of the instruction or instruction word depends on thespecific computer design. FIG. 1 shows a typical instruction word 101.The instruction word includes an opcode field 110 and one or moreoperand fields 115, depending on the instruction. The opcode defines theoperation and the operand or operands may contain data that are to beoperated by the given instruction.

Various types of computer architectures exist, such as Von-Neumann andthe Harvard Architectures. See generally Hennessy and Pallerson,Computer Architecture: A Quantitative Approach (1996), which is hereinincorporated by reference for all purposes. In the Von-NeumannArchitecture, both data and instructions are transmitted between theprocessor and memory by a bi-directional bus. As such, the instructionstream includes both data and instructions. In contrast, instructionsand data are transmitted on separate buses in the Harvard Architecture,separating the data from the instruction stream.

An instruction requiring an operand that is a constant known at compiletime is referred to as an immediate instruction. The known operand isreferred to as an immediate data. Immediate data often results insituations where an instruction is operating on a constant or where theoperand is an address pointer.

In all current processors, regardless of the architecture, immediatedata is included as part of the instruction word (stored in the operandfield 115 of the instruction word). That is, the immediate data is partof the instruction stream. In some instances, the length of theimmediate data can exceed the length of the operand field of theinstruction word. Immediate data which exceeds the length of the operandfield is typically referred to as a long immediate data. To accommodatethe long immediate data, an extension 220 is provided in the instructionword 101, as shown in FIG. 2. The instruction extension is essentiallyan instruction word containing the immediate data that follows theinstruction word 101. As such, an additional cycle is required to handlethe extension of a long immediate data.

The presence of extensions can complicate decoding and pipeliningissues. To avoid extensions, either constraints are imposed to limit thelength of immediate data or the instruction word comprises an operandfield having a sufficient length to handle the widest possible immediatedata. In the first case, imposing constraints on the length of immediatedata may not be desirable due to application requirements. For example,in digital signal processing (DSP) applications, the length of theimmediate data is often governed by domain characteristics such assignal-to-noise (SNR) requirements. Likewise, increasing the length ofthe instruction word to handle the long immediate data may beundesirable as this leads to inefficient use of memory, particularlywith embedded systems where chip size is a major concern.

As evidenced by the foregoing discussion, it is desirable to improvecoding efficiency without imposing constraints on the length immediatedata.

SUMMARY OF THE INVENTION

In one embodiment, the processor includes a program counter which storesan instruction address. The instruction at the instruction address isfetched by the processor and decoded. If the decoded instructioncomprises an immediate instruction, the corresponding immediate data isfetched from a data table.

In one embodiment, immediate data is stored in the data table in theorder determined by a flow analysis. The flow analysis identifiesimmediate instructions and stores the corresponding immediate data inthe program order of the immediate instructions. In one embodiment, theflow analysis identifies immediate instructions and stores thecorresponding immediate data in substantially the program order of theimmediate instructions, taking branching into account. The informationprovided by the flow analysis is used to generate instruction coding toenable retrieval of the immediate data from the data table.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an instruction word;

FIG. 2 shows an immediate instruction word which includes an instructionextension;

FIG. 3 shows a static flow analysis in accordance with one embodiment ofthe invention;

FIG. 4 shows a static flow analysis in accordance with anotherembodiment of the invention;

FIGS. 5–6 illustrate the concept of outermost sections in accordancewith the invention;

FIG. 7 shows the placement of immediate data from the program into a DTin accordance with one embodiment of the invention;

FIG. 8 illustrates a flow analysis in accordance with another embodimentof the invention;

FIG. 9 shows a process for operating a processor in accordance with oneembodiment of the invention;

FIG. 10 shows a processor in accordance with one embodiment of theinvention;

FIG. 11 illustrates the instruction coding in accordance with oneembodiment of the invention;

FIG. 12 shows a process for operating a processor in accordance withanother embodiment of the invention;

FIG. 13 shows a processor in accordance with another embodiment of theinvention; and

FIG. 14 shows a processor in accordance with yet another embodiment ofthe invention.

DESCRIPTION OF THE INVENTION

The present invention relates generally to a coding scheme for handlingimmediate data in a computer program, which makes efficient use ofmemory without imposing programming constraints. A processor, such as amicroprocessor, a microcontroller, a digital signal processor (DSP), oran embedded system, executes the program. The present invention isparticularly useful for handling immediate data in the processor'sfirmware.

The computer program can be generated using high-level computerlanguages, such as C++. Other high level languages are also useful. Theprogram is processed to translate it into machine code usable by theprocessor. The program may be processed in several stages before it isfinally translated into machine code. For example, most compilersinitially process the program to generate assembly code. An assemblerthen translates the code into machine code which is then stored intomemory for use by the processor.

In accordance with the invention, a coding scheme that separatesimmediate data from the instruction stream is disclosed. As used herein,the term “immediate data” can refer to long immediate data or immediatedata in general. Such a coding scheme eliminates instruction extensionswithout increasing the length of the instruction word or imposingconstraints on programming, thus improving coding density and processingefficiency.

In one embodiment, the separation of immediate data from the instructionstream is facilitated by a static control flow analysis to identify anddetermine an order of the immediate data in the program. Immediate dataare stored in a data table in the order determined by the flow analysis.The coding of an immediate instruction can include addressinginformation for retrieval of the immediate data by the processor whenthe immediate instruction is executed.

A post-processor, for example, performs the flow analysis. Thepost-processor can be incorporated as a part of a compiler, anassembler, or a tool used to translate higher level codes into lower ormachine level codes. Providing a post-processor which is separate fromthe tools used to translate higher level codes into lower level codes isalso useful.

FIG. 3 shows a flow analysis in accordance with one embodiment of theinvention. The flow analysis facilitates the separation of immediatedata from the instruction stream. The flow analysis, for example,creates a model of a data table comprising immediate data of theimmediate instructions from a program.

In one embodiment, the flow analysis identifies an immediate instructionin the program at step 310. At step 320, the immediate data of theimmediate instruction is assigned a location in a separate storage thatis accessible by the processor. The assignment of location can beexplicit (e.g., assigning a specific location) or implicit (e.g., byplacement of immediate data in the model). The separate storage, forexample, comprises a read only memory (ROM) table or other memorystorage locations. The separate storage is referred to as a data table(DT). The flow analysis also generates addressing information to enableretrieval of the immediate data when the processor executes theinstruction. At step 330, the flow analysis continues the process ofidentifying immediate data and assigning a location in the DT until allimmediate data in the program are identified. At step 340, the flowanalysis is completed once all immediate data have been identified.

The information generated by the flow analysis, such as the model of theDT, is used to replicate the actual DT. For example, the flow analysisprovides the information that enables the storing or burning (for ROM)of the immediate data into the DT at their assigned addresses duringchip design or fabrication. The flow analysis can also provide thefunction of creating the DT.

The information provided by the flow analysis can also be used togenerate the instruction coding to retrieve the immediate data from theDT. The post-processor that performs the flow analysis can provide thefunction of generating the instruction coding. A separate post-processorthat provides the instruction coding can also be useful. In a preferredembodiment, the flow analysis identifies the immediate data in theirprogram execution order (program order) and assigns DT addresses to theimmediate data to reflect their program order. In one embodiment, theflow analysis provides a systematic approach to identify immediate datain substantially their program order, taking into account of branches,i.e., conditionally executed instructions.

FIG. 4 shows another embodiment of the static flow analysis. As shown,the flow analysis commences at step 410 by grouping the program codesinto outermost sections. At step 420, the flow analysis identifiesimmediate data within an outermost section and assigns correspondinglocations in the DT at step 430. The flow analysis also generatesaddressing information to enable retrieval of the immediate data whenthe processor executes the instruction. At step 440, the flow analysisdetermines whether there are more outermost sections that need to beanalyzed. If there are more outermost sections that need to be analyzed,the flow analysis returns to step 420. Otherwise, the flow analysisfinishes at step 450.

To understand the concept of outermost sections, the term section isfirst defined. A typical program comprises a plurality of codes andbranches. A section refers to an atomic unit of the program and isdefined as one or more instructions or codes in a program path betweentwo branch nodes or points. A branch node or point can refer to eitherthe start or the end of a branch. An unconditional section refers to asection whose codes are all unconditionally executed during programexecution. On the other hand, a section whose codes may not be executedduring program execution is referred to as a conditional section.

An outermost section is defined as either an unconditional section or agroup of conditional sections between corresponding start and end branchnodes that are unconditionally encountered during program execution. Anoutermost section that comprises an unconditional section is referred toas an unconditional outermost section. An outermost section thatcomprises a group of conditional sections is referred to as aconditional outermost section. From the definitions provided, aconditional outermost section comprises at least two conditionalsections. In some instances, a conditional outermost section cancomprise a plurality of conditional sections having numerous branchestherein.

FIGS. 5–6 show a sample program 501 to facilitate understanding of thestatic flow analysis in accordance with one embodiment of the invention.Referring to FIG. 5, the program includes a plurality of codes andbranches. A start of a branch is represented with arrows splitting offinto two different paths of the program, and an end of a branch isrepresented with arrows merging into one path. The codes are groupedinto sections 510, 521, 522, 530, 541–547, 551–554, and 560. A dashedline within a section represents an immediate instruction.

Referring to FIG. 6, the program 501 is grouped into outermost sections.Applying the rules pertaining to outermost sections, sections 510, 530,and 560 are categorized as outermost sections since they areunconditional sections. Sections 521 and 522 are grouped as an outermostsection 610 because they are located between corresponding unconditionalstart and end branch points 624 and 625. Likewise, conditional sections541–547 and 551–554 are grouped as an outermost section 640 since thoseconditional sections are located between corresponding unconditionalstart and end branch points 650 and 651.

In an embodiment of the invention, the static flow analysis identifiesimmediate data within an outermost section one outermost section at atime. In a preferred embodiment, the flow analysis identifies immediatedata from the outermost sections in the program order of the outermostsections. The immediate data are assigned DT addresses to reflect theoutermost sections' program order. More preferably, immediate datawithin an outermost section are identified in their program order andassigned DT addresses to reflect their program order within theoutermost section. Analyzing outermost sections in other orders andassigning addresses to reflect other orders can also be useful.

FIG. 7 illustrates the placement of immediate data from the program 501into a DT table 701 in accordance with one embodiment of the invention.As shown, the program is grouped into outermost sections. The programorder of the outermost sections is 510, 610, 530, 640, 560. Sinceoutermost section 510 is first in the program order, the immediate datacorresponding to the immediate instructions therein are assigned andstored in addresses of the first region 710 of the DT. Subsequentoutermost sections 610, 530, 640, and 560 occupy subsequent regions 720,730, 740, and 750, respectively, of the DT.

As previously described, an unconditional outermost section comprisesmore than one conditional sections. In one embodiment of the invention,the flow analysis handles a conditional outermost section by separatingit into right and left subsections. One subsection is analyzed firstbefore analyzing the other. In one embodiment, the flow analysisanalyzes the right subsection first and then the left subsection.Immediate data in the right subsection are identified and assigned DTaddresses first and then immediate data in the left subsection areidentified and assigned DT addresses. The DT addresses preferablyreflect the program order of the immediate data within the subsection.Analyzing the left subsection first and then the right subsection isalso useful. In a preferred embodiment, the order in which thesubsection is analyzed is consistent for all the outermost sections.

A subsection of an outermost section can comprise a plurality ofconditional sections. In such a case, the subsection can be grouped intooutermost sections as viewed within the subsection. The immediate datawithin an outermost section preferably are identified and assigned DTaddresses to reflect their program order within the outermost sections,as previously described. In this manner, the program is recursivelyanalyzed to construct the DT. Thus, the immediate data are analyzed andassigned DT addresses to reflect substantially their program order,taking branching into account.

FIG. 8 illustrates the recursive construction of DT by the flowanalysis. Similar to FIG. 7, the program 501 comprises outermostsections having a program order of 510, 610, 530, 640, and 560. Theimmediate data of the outermost sections are assigned DT addresses toreflect the program order of the outermost sections. Immediate data fromoutermost sections 510, 610, 530, 640, and 560 are assigned addresses inDT regions 710, 720, 730, 740, and 750, respectively.

Outermost section 610, which comprises sections 521 and 522, isseparated into right and left subsections. Sections 521 and 522 can beviewed as outermost sections within their respective subsections (i.e.,they unconditional sections within their respective subsections). Inaccordance with one embodiment, the right section is analyzed before theleft section, resulting in the storing of immediate data from the rightsubsection in portion 822 of DT region 720 and the storing of immediatedata from the left subsection in portion 823.

Outermost section 640 is also separated into right and left subsections810 and 850 and their immediate data are stored in portions 862 and 863,respectively, of the DT region 740.

The right subsection comprises a plurality of sections which can begrouped into outermost sections with respect to the subsection. Sections541 and 547 are outermost sections since they are consideredunconditional sections; sections 542–546 are grouped as an outermostsection 830 since they are located between corresponding unconditionalstart and end branch points 821 and 822. Immediate data from outermostsections 541, 830, and 547 of the right subsection are stored inportions 870, 883, and 876 of DT region 740.

Outermost section 830 can be further separated into right and leftsubsections. As such, the analysis is recursively applied to the programcode to group the code into outermost sections and separate them intoright and left subsections. The recursive analysis, in accordance withone embodiment of the invention, results in assigning DT addresses forthe immediate data from sections 542, 543, 544, 545, and 546 insubportions 871, 872, 873, 874, and 875 of the portion 883.

After immediate data from the right subsection 810 have been assigned DTaddresses, the left subsection 850 is analyzed. The analysis, which issimilar to that of the right subsection, groups the codes into outermostsections 551, 840, and 554. The immediate data from the outermostsections are assigned DT addresses in portion 863 of DT region 740 toreflect their program order. In particular, immediate data fromoutermost section 551 are stored in portion 877, immediate data fromoutermost section 840 are stored in portion 885, and immediate data fromoutermost section 554 are stored in portion 880. Outermost section 840can be separated into right and left subsections. The right subsectioncomprises section 552 and the left subsection comprises section 553.Immediate data from the right subsection are stored in subportion 878and immediate data from the left subsection are stored in subportion879.

In one embodiment, a subroutine Build_DT recursively analyzes theprogram and creates a model of a DT with its contents. The informationproduced by the Build_DT routine can be, for example, provided toanother tool to create the DT. An example of the subroutine Build_DT isas follows:

Build_DT(section, total_outermost_sections)

for i=0 . . . total_outermost_sections−1)

-   -   Place (outersection(i));

endfor

end Build_DT

As shown, Build_DT routine receives parameters section andtotal_outermost_sections. The section parameter represents the sectionto be placed (which is initially the whole program), and thetotal_outermost_sections parameter represents the number of outermostsections within the program. The routine analyzes the outermost sectionsin the program order of the outermost sections, starting from the firstone (i=0) to the last one (total_outermost_section−1). For eachoutermost section, Build_DT calls a routine Place to store the immediatedata into the DT. In one embodiment, Place stores the immediate datainto the DT in their program order within the outermost section.

An example of the Place subroutine is as follows:

Place (section)

if section is unconditional

-   -   place all the immediates required by routine    -   in their data order in the DT.

else

-   -   Build_DT(section.right,        -   get_outermost(section.right))    -   Build_DT(section.left,        -   get_outermost(section.left))

endif

end Place

The subroutine Place analyzes the outermost section to determine whetherit is a conditional or an unconditional outermost section. Anunconditional outermost section indicates that it contains one section.If an unconditional outermost section is detected, the routine storesthe section's immediate data in the DT. The immediate data are stored intheir program order or in the order in which they are identified. Onceall immediate data within the outermost section are stored in the DT,the Place routine terminates and returns to the Build_DT routine tocontinue analyzing the next outermost section, if any.

A conditional outermost section, on the other hand, indicates that thereexists a plurality of sections. When a conditional outermost section isencountered, the Place routine separates the outermost section intoright and left subsections and analyzes each one individually.Illustratively, the Place routine analyzes the right subsection and thenthe left subsection.

The Place routine calls the Build_DT routine to analyze the subsection.Simultaneously, a routine get_outermost is invoked to find the outermostsections within the subsection. As such, Place views each subsection asif it were a separate program and analyzes accordingly. In this manner,the post-processor recursively analyzes the program to construct the DTmodel.

The flow analysis also provides information to generate the instructioncoding for handling the separation of immediate data from theinstruction stream. In accordance with the invention, the flow analysisprovides addressing information related to the immediate data in the DT.Such addressing information can be in the form of relative or absoluteaddressing information. For relative addressing, the flow analysis mayperform more than one pass to obtain the addressing information. As anexample, a first pass may be used to compute the sections andsubsections while a second pass is used to assign the offset forrelative addressing of the immediate data.

The addressing information generated by the flow analysis can be usedby, for example, a compiler or an assembler to generate the instructioncoding to accommodate the use of a DT. In one embodiment, theinstruction coding informs the processor that the current instructionneeds an immediate data as well as addressing information to retrievethe immediate data. Indicating that an immediate data is needed can beachieved by, for example, providing a bit in the instruction to serve asa flag to indicate that an immediate data is needed. Alternatively, theprocessor could be informed implicitly by embedding the request forimmediate data in the opcode. The addressing information identifying thelocation of the immediate data can be stored in the operand field of theinstruction word. The information is transferred to and used by the DTpointer to access the DT for retrieving the immediate data. In oneembodiment, the addressing information contains absolute addressing.

FIG. 9 shows a process for operating a processor in accordance with oneembodiment of the invention. The processor fetches an instruction atstep 910. For example, at the beginning of program execution, theprogram counter is reset to 0 to point to the first instruction. Theprocessor fetches the instruction to which the program counter points.At step 920, the processor determines whether the instruction is animmediate instruction or not. If it is not an immediate instruction, theprocessor proceeds to step 950 for instruction execution. If theinstruction is an immediate instruction, the addressing informationstored in the operand field is loaded into a DT pointer at step 930. Atstep 940, the processor retrieves the immediate data in the DT at theaddress provided by the DT pointer and executes the instruction at step950. At step 960, the processor determines if the program is completed.If the program is not completed, the next instruction is fetched at step910. The process continues until all instructions have been executed,terminating the program at step 970.

FIG. 10 shows a processor 10 in accordance with one embodiment of theinvention. The processor can comprise a Von-Neuman or Harvardarchitecture. Other processor architectures are also useful. As shown,the processor comprises a program counter 30. The program counter iscoupled to the memory (not shown) which stores the program. The programpointer points to the instruction that is to be fetched for execution.The instruction is fetched from memory and stored in the instructionregister (IR) 35. An instruction decoder (ID) 31 decodes the instructionin the IR. If the ID determines that it is an immediate instruction, itactivates a DT pointer 60 and a DT 50, causing the addressinginformation stored in the operand field of the immediate instructionword to be loaded into the DT pointer. The immediate data at the addresscontained in the DT pointer is made available to the processor forexecuting the immediate instruction. Alternatively, the addressinginformation can be used directly to access the DT, avoiding the need ofa DT pointer.

In another embodiment of the invention, the coding uses relativeaddressing information. The relative addressing information comprises anoffset that is used to address the immediate data in the DT. In oneembodiment, the offset is with respect to the DT address of theimmediate data from the previously executed immediate instruction.Employing the use of relative addressing advantageously reduces thenumber of bits needed to address the DT, particular for applicationswith a very large number of DT entries.

In accordance with one embodiment of the invention, the DT pointer isreset to a value that points to the first entry in the DT at the end ofprogram execution or prior to the commencement of program execution. Forexample, the DT pointer is reset to zero.

The offset modifies the DT pointer for addressing the DT. In oneembodiment, the offset is added to the current value stored in the DTpointer. To accommodate branching in the program, a pre/post bit isprovided to indicate whether a pre-offset or post-offset format is used.This results in an instruction coding in which the operand field of animmediate instruction word comprises the format (pre/post, #offset). Inone embodiment, a pre/post bit having a value of 1 represents apre-offset format, and a 0 value represents a post-offset format. In thepre-offset, the offset is added to the current value of the DT pointer(current value+offset) before retrieving the immediate data from the DT.After the immediate data is retrieved, the value in the DT isincremented to point to the DT address containing the immediate data ofthe next immediate instruction. For example, the DT printer isincremented by 1 (current value+offset+1). In the post-offset format,the current value of the DT pointer (current value) is used to retrieveimmediate data from the DT. The DT pointer is incremented, for example,by 1 (current value+1) after the immediate data is retrieved to point tothe immediate data of the next immediate instruction.

In accordance with one embodiment of the invention, the coding of thepre/post bit and offset value depends on whether the section isconditional or unconditional. For unconditional sections, the immediateinstructions have a coding wherein the pre/post bit indicates that theoffset is added after instruction execution (post) and the offset value(#offset) is 1. The term “unconditional sections” also refers toconditional sections which are viewed as unconditional sections within asubsection.

As for conditional sections, the last immediate instruction of a rightsubsection has a coding format in which the pre/post bit indicates thatthe offset is added after instruction execution and the offset value isequal to the number of immediate instructions on the left subsection+1.The first instruction of the left subsection has a coding in which thepre/post bit indicates that the offset is added before instructionexecution (pre) and the offset value is equal to the number of immediateinstructions in the right subsection. All other immediate instructionshave pre/post bit equal to post and offset equal to 1. The lastimmediate instruction in the program is always coded to reset the DTpointer to zero (i.e., beginning of the DT). This can be done by settingthe offset value to zero while the value of pre/post bit has no effect(don't care).

As described, the maximum value (m) of the offset within a program inthe case where the right subsection is analyzed first is equal either tothe maximum number of immediate instructions in a right outermostsubsection or to the number of immediate instructions in the leftoutermost subsection+1, whichever is greater. The number of bits neededto code the offset in the immediate instructions is equal to┌log₂(m+1)┐. The total number of bits needed in the operand field tocode an immediate instruction is equal to 1+┌log₂(m+2)┐, where theadditional bit is for the pre/post flag. In some cases, the coding mayinclude an additional bit to explicitly instruct the processor that thecurrent instruction is an immediate instruction. In most embeddedapplications, especially in data-intensive DSP, the value of m isrelatively small, such as less than 8. For m=8, the number of operandbits required is at most 5 bits (4 for the offset, 1 for the pre/post).In the case where an immediate instruction is identified explicitly bythe use of a bit, only an additional bit is needed. This cansignificantly reduce the number of bits needed in the operand field tohandle immediate data and eliminate the need for instruction extensions,resulting in more efficient coding.

FIG. 11 illustrates the coding in accordance with one embodiment of theinvention. As shown, the program 501 is grouped into outermost sections510, 610, 530, 640, and 560. A dashed box indicates an atomic unit orsection. An immediate instruction within the section is represented by anumber whose value indicates its program order within the section. Thecoding for the immediate instruction is enclosed in brackets. A post orpre indicates that the offset is added after or before instructionexecution, and the value after # indicates the offset. An alternatingshort and long dashed box represents a right or left subsection. Thenumber on top of each subsection reflects the number of immediateinstructions within the subsection.

For unconditional outermost sections 510 and 530, the immediateinstructions are coded (post, #1). The last immediate instruction of theprogram, which is located in outermost section 560, is coded (pre/post,#0) to reset the DT pointer to zero. Outermost section 610 is separatedinto right and left subsections. The right subsection comprises section521 and the left subsection comprises section 522. The last immediateinstruction in the right subsection is coded (post, #8) to provide anoffset of 8 (7 instructions on the left subsection+1). The firstinstruction on the left section is coded (pre, #6).

As for outermost section 640, the right and left subsections 810 and 850each comprises a plurality of sections. The sections within eachsubsection are recursively analyzed, grouping the sections intooutermost sections and separating the outermost sections into right andleft subsections, if necessary. For example, the right subsection 810 isgrouped into outermost sections 541, 830, and 547. Outermost section 830can further be separated into right and left subsections 110 and 150.The immediate instructions are coded as previously described.

FIG. 12 shows a process for operating a processor in accordance withanother embodiment of the invention. At the beginning of programexecution at step 210, the DT pointer is reset to zero to point to thefirst entry in the DT. The program counter is also reset to point to thefirst instruction. At step 220, the processor fetches the instruction towhich the program counter points. At step 230, the processor determineswhether the instruction is an immediate instruction or not. If it is notan immediate instruction, the processor proceeds to step 280 forinstruction execution. If the instruction is an immediate instruction,the processor further determines if the offset information stored in theoperand field is pre-format or post-format at step 240. Also, theprocessor can analyze the offset to see if it is equal to zero or not,indicating whether or not there are any more immediate instructions. Azero offset resets the DT pointer to zero. If the offset is post-formatcoded, the process proceeds to step 250. At step 250, the current valuein the DT pointer is used to retrieve the immediate data in the DT. Theinstruction is executed at step 255. After instruction execution, theoffset is added to the current value in the DT pointer and storedtherein at step 252. If the offset is pre-format coded, the processproceeds to step 260. At step 260, the offset is added to the currentvalue of the DT pointer and the new value is used to retrieve theimmediate data in the DT at step 261. At step 262, the processorexecutes the immediate instruction. The DT pointer is then incrementedby 1 at step 263. At step 290, the processor determines if there areanymore instructions. If there are, the next instruction is fetched atstep 220. The process continues until all instructions have beenexecuted, terminating the program at step 295.

FIG. 13 shows a processor 310 in accordance with one embodiment of theinvention. As shown, the processor comprises a program counter 330. Theprogram counter is coupled to the memory (not shown) which stores theprogram. The program pointer points to an instruction. The instructionis fetched from memory and stored in an IR 335. An ID 331 decodes theinstruction in the IR. If the ID determines that it is an immediateinstruction, it activates a DT addressing unit 360 and DT 350. The DTaddressing unit comprises a DT pointer 361, which receives theaddressing information from the instruction. The addressing informationin the DT pointer is used to fetch the immediate data from the DT foruse by the processor.

The immediate instruction provides relative addressing information toidentify the location of the immediate data in the DT. In oneembodiment, the relative addressing information includes an offset and apre/post bit. If the pre/post bit represents a post-offset, the DTaddressing unit uses the current value in the DT pointer to address theDT to retrieve the immediate data. The offset is added to the currentvalue of the DT pointer after the immediate data is fetched. If thepre/post bit represents a pre-offset, the DT addressing unit adds theoffset to the current value of the DT pointer. The new value in the DTpointer is used to fetch the immediate data. After the immediate data isfetched, the DT is incremented by 1 to point to another addresscontaining the immediate data of, for example, the next immediateinstruction. As shown, a pre/post value of 1 represents pre-offset, anda pre/post value of 0 represents post-offset.

In one embodiment, the addressing unit comprises adders 363 and 364, theDT pointer, and a multiplexer 368. Adder 363 receives as inputs theoffset value from the IR and the current value in the DT pointer. Theoutput of adder 363 is coupled to adder 364. Also coupled to adder 364is the pre/post bit. The output of adder 364 is coupled to the DTpointer, whose output is coupled to the multiplexer 368. The pre/postbit also serves as a select signal for the multiplexer.

In operation, adder 363 adds the offset to the current value in the DTpointer. The result of adder 363 is passed to both the adder 364 and tothe multiplexer 368. A pre/post bit equal to 1 indicates a pre-offsetaddressing of the DT, causing the multiplexer to select the sum of theoffset and current value of the DT pointer (current DT printer+offset)as the DT address containing the immediate data. Adder 364 then adds theresults of adder 363 to the pre/post bit, which is 1. The result(offset+current DT pointer+1) is then loaded into the DT pointer for thenext DT access.

A pre/post bit equal to 0 indicates a post-offset addressing of the DT.This causes the multiplexer to select the value of the current DTpointer to access the DT. After the immediate data is fetched from theDT, adder 363 adds the current DT value to the offset (current DTpointer+offset) whose result is then added by adder 364 to the pre/postbit, which is equal to 0. The result of adder 364 (current DTpointer+offset) is then loaded into the DT pointer to use for the nextDT access.

In the case where the program does not include branching, the pre/postbit can be eliminated. Additionally, the instruction coding need onlyidentify that the instruction is an immediate instruction. This isbecause the offset is always 1 if the immediate data is stored in theirprogram order. By creating a scenario in which the offset is constantfor all immediate instructions, the DT addressing unit can be configuredto provide the offset. Thus, the need for offset information in theinstruction coding can be avoided.

FIG. 14 shows an embodiment of a processor for handing coding withoutbranching. As shown, the processor 410 comprises a program counter 430.The program counter is coupled to the memory (not shown) which storesthe program. The program pointer points to an instruction that is to beexecuted. The instruction is fetched from memory and stored in the IR435. An ID 431 decodes the instruction in the IR. If the ID determinesthat it is an immediate instruction, it activates a DT addressing unit460 and a DT 450. The immediate data stored in the location referencedby a DT pointer 464 in the DT addressing unit is fetched for theprocessor's use. After the immediate data is fetched, the current valuein the DT pointer is incremented by 1 using an adder 465 in the DTaddressing unit.

While the invention has been particularly shown and described withreference to various embodiments, it will be recognized by those skilledin the art that modifications and changes may be made to the presentinvention without departing from its scope. The scope of the inventionshould therefore be determined not with reference to the abovedescription but with reference to the appended claims along with theirfull scope of equivalents.

1. A processor comprising: instructions with at least one operand field,the instructions comprises immediate instructions having immediate datain the operand field; a data table for storing immediate data, whereinimmediate data are stored in the data table in an order determined by aflow analysis, the data table enables immediate data to be separatedfrom the instruction stream; a program counter for storing aninstruction address of an instruction, wherein the processor fetches aninstruction from the instruction address in the program counter duringprogram execution; an instruction decoder for decoding the instructionfetched by the processor, wherein immediate data from the data table isprovided to the processor if the instruction fetched is an immediateinstruction; an instruction register coupled to the instruction decoder,the instruction register stores the instruction fetched by the processorduring program execution and passes the instruction to the instructiondecoder for decoding; and a data table addressing unit coupled to thedata table and the instruction register, the instruction registerpassing relative addressing information contained in the instruction tothe data table addressing unit when the decoder decodes the immediateinstruction, the relative addressing information, which comprises anindex and a format indicator, is used to provide an address of theimmediate data in the data table, wherein the data addressing unitcomprises a data table pointer containing a value, if the formatindicator comprises a post-format, the value serves as the address andafter the immediate data is provided to the processor, the index isadded to the value to produce a new value in the data table pointer fora next immediate instruction, if the format indicator comprises apre-format, the index is added to the value to produce the address tothe immediate data and the address is incremented by 1 after theimmediate data is provided to the processor to produce a new value inthe data table pointer for the next immediate instruction, the formatindicator comprises a binary bit having a logic 1 and logic 0 value, thelogic 1 indicating one of pre-format or post-format and the logic 0indicating other of pre-format or post-format, the data table addressingunit further comprising, a first adder comprising a first input coupledto the instruction register for receiving the index and a second inputcoupled to an output of the data table pointer for receiving the valuecontained therein, a second adder comprising a first input coupled tothe instruction register for receiving the format indicator, a secondinput coupled to an output of the first adder, and an output coupled tothe data table pointer, and a multiplexor comprising a first inputcoupled to an output of the data table pointer, a second input coupledto the output of the first adder, and a select input coupled to theinstruction register for receiving the format indicator to select anmultiplexor output from the first and second multiplexor inputs.
 2. Theprocessor of claim 1 wherein the data table addressing unit comprises anincrementor for incrementing the address after the immediate data isprovided to produce a new address for a new immediate instruction. 3.The processor of claim 1 or 2 wherein the flow analysis comprises astatic flow analysis, the static flow analysis to identifies immediateinstructions within a program.
 4. The processor of claim 3 wherein animmediate instruction comprises addressing information to enable theprocessor to retrieve a corresponding immediate data to the immediateinstruction.
 5. The processor of claim 4 wherein the addressinginformation comprises absolute addressing information.
 6. The processorof claim 4 wherein the addressing information comprises relativeaddressing information.
 7. A processor comprising: a data table forstoring immediate data of immediate instructions; a program counter forstoring an instruction address of an instruction, wherein the processorfetches the instruction from the instruction address in the programcounter during program execution; and an instruction decoder fordecoding the instruction fetched by the processor, wherein immediatedata from the data table is provided to the processor if the instructionis an immediate instruction; an instruction register coupled to theinstruction decoder, the instruction register stores the instructionfetched by the processor during program execution and passes theinstruction to the instruction decoder for decoding; a data tableaddressing unit comprising a data table pointer containing a value, thedata table is coupled to the data table and instruction register, theinstruction register passing relative addressing information containedin the instruction to the data table addressing unit when the decoderdecodes the immediate instruction, the relative addressing information,which comprises an index and a format indicator, is used to provide anaddress of the immediate data in the data table, wherein the formatindicator comprises a binary bit having a logic 1 and logic 0 value, thelogic 1 indicating one of a pre-format or a post-format and the logic 0indicating other of the pre-format or post-format; if the formatindicator indicates the post-format, the value serves as the address andafter the immediate data is provided to the processor, the index isadded to the value to produce a new value in the data table pointer fora next immediate instruction and if the format indicator indicates thepre-format, the index is added to the value to produce the address tothe immediate data and the address is incremented by 1 after theimmediate data is provided to the processor to produce a new value inthe data table pointer for the next immediate instruction; and whereinthe addressing unit comprises a first adder comprising a first inputcoupled to the instruction register for receiving the index and a secondinput coupled to an output of the data table pointer for receiving thevalue contained therein, a second adder comprising a first input coupledto the instruction register for receiving the format indicator, a secondinput coupled to an output of the first adder, and an output coupled tothe data table pointer, and a multiplexor comprising a first inputcoupled to an output of the data table pointer, a second input coupledto the output of the first adder, and a select input coupled to theinstruction register for receiving the format indicator to select anmultiplexor output from the first and second multiplexor inputs.
 8. Aprocessor comprising: a data table for storing immediate data ofimmediate instructions; a program counter for storing an instructionaddress of an instruction, wherein the processor fetches the instructionfrom the instruction address in the program counter during programexecution; and an instruction decoder for decoding the instructionfetched by the processor, wherein immediate data from the data table isprovided to the processor if the instruction is an immediateinstruction; an instruction register coupled to the instruction decoder,the instruction register stores the instruction fetched by the processorduring program execution and passes the instruction to the instructiondecoder for decoding; a data table addressing unit comprising a datatable pointer having a value, the data table addressing unit receivesrelative addressing information for decoded immediate instructions, therelative addressing information, which comprises an index and a formatindicator, is used to provide an address of the immediate data in thedata table; if the format indicator indicates a post-format, the valueserves as the address and after the immediate data is provided to theprocessor, the index is added to the value to produce a new value in thedata table pointer for a next immediate instruction and if the formatindicator indicates a pre-format, the index is added to the value toproduce the address to the immediate data and the address is incrementedby 1 after the immediate data is provided to the processor to produce anew value in the data table pointer for the next immediate instruction;and wherein the addressing unit comprises a first adder comprising afirst input coupled to the instruction register for receiving the offsetand a second input coupled to an output of the data table pointer forreceiving the value contained therein, a second adder comprising a firstinput coupled to the instruction register for receiving the formatindicator, a second input coupled to an output of the first adder, andan output coupled to the data table pointer, and a multiplexorcomprising a first input coupled to an output of the data table pointer,a second input coupled to the output of the first adder, and a selectinput coupled to the instruction register for receiving the formatindicator to select an multiplexor output from the first and secondmultiplexor inputs.